1. Field of the Invention
The field of the invention relates to data processing and in particular to applying resets to a data processing apparatus.
2. Description of the Prior Art
The application of a reset to a data processing apparatus is known. This reset signal may be an asynchronous signal and therefore it may need to be synchronised to the processor's clock domain. Conventional reset synchroniser circuits are known in microprocessor designs that have a single reset input. It is also known for processors that have multiple reset inputs for these inputs to be synchronised with respect to the device they are resetting. However, there is generally no interconnection between such multiple reset inputs or their synchronisation.
The application of two independent resets to a data processing apparatus is used, for example, in a processor that has some diagnostic function such as debug circuitry. Such a processor typically requires two independent resets, a system reset and a diagnostic reset. This allows the system logic to be reset independently of the diagnostic logic, thereby enabling a system to be monitored through application of a system reset. In such a system both resets will typically need to be applied at system power-on and typically the system reset will also need to be a superset of the diagnostic reset, in other words if the diagnostic reset is driven, then the system reset must also be driven.
At power on the system reset may be delayed by a reset controller in response to detection of the processing apparatus not being ready, a PLL not being locked for example. As the two resets are independent and may be synchronised independently then the diagnostic reset may not be similarly delayed and diagnosis, for example debug, may start before the system is ready to operate, e.g. PLL is not locked. This can lead to errors. It would be advantageous to avoid this problem, while maintaining the possibility to reset either the system or the diagnostic circuitry independently of each other.